Embodiments of the application described herein relate to a timing matching method of a timing analyzer and a method of designing an integrated circuit using the same.
A memory device, an application specific random access memory (ASIC), etc. are released to the market through a series of steps, such as design and process steps of a semiconductor circuit, a chip test step, and a test step after packaging the semiconductor circuit. In order to search for a timing error which occurs on a circuit in a very large scale integration (VLSI) design, there are a dynamic timing analysis (DTA), a static timing analysis (STA), etc.
In the DTA, a timing relation between memory devices in a circuit is studied by applying a test stimulus of a certain type to the circuit. Accordingly, weak points of the circuit are searched for and mitigated.
In the STA, paths which may perform unstable operations are searched for and analyzed in consideration of all signal transmission paths which exist among memory devices configuring a circuit, without applying a test stimulus of a specific type to the circuit. In the STA, timing between signals input and output to or from a designed semiconductor memory or logic is analyzed, and thus the designed semiconductor circuit or logic is tested about whether it may be normally operated without a problem in the timing.
The STA is performed by an STA tool (e.g., PrimeTime). If the designed semiconductor circuit or logic is input in the STA tool, the STA tool extracts delay models corresponding to the input semiconductor circuit or logic from delay models for various cells stored in its database, such as transistors, cells of a gate level, cells of a unit logic (e.g., AND, OR, etc.) level, or cells of special functions (e.g., sense amplifier-based flip flops, etc. in which it is difficult to compute a delay between input and output). The STA tool analyzes timing between input and output signals and reports delay values among nodes which exit in the semiconductor circuit or logic.